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CH572 has no port B. CH573, CH582 and CH583 have no Px_SET, so a high output goes through Px_OUT. PB22 and PB23 are armed only where PIN_INTX exists, and the port handler reads each interrupt register once.

PB16 and PB17 swap while PB22 is held, so a press is visible without RTT.

I2C0 runs at Fsys with the vendor clock formula, up to 400 kHz, on PB13/PB12 or the remapped PB21/PB20 pair. Transfers poll STAR1 with a one millisecond timeout and follow the STM32-style NACK and STOP sequence. Async transfers and bus recovery are not included.

i2c_scan probes PB13/PB12 at 100 kHz and logs every address that answers. i2c_oled drives the SSD1306 found at 0x3C at 400 kHz, drawing a banner, a bouncing circle and two text lines through embedded-graphics.

SPI0 and SPI1 run at Fsys with a whole-number divisor, in mode 0 or mode 3. A full-duplex transfer writes FIFO and reads the shifted-in byte from BUFFER; FIFO_DIR is a receive buffer and drops the byte just sent. The module compiles only for the CH585 FIFO layout. Async transfers, DMA and slave mode are not included.

spi_loopback joins PA14 to PA15 and checks a 10-byte mode 0 transfer, then a 40-byte mode 3 transfer, against what was sent. PA12 is driven as a chip select.

The converter polls one channel at a time on the CH585 register layout, with the internal temperature sensor and the divided battery channel. An external pin has its digital input disconnected first. Scan, DMA and touch-key modes are not included.

adc_temp reads the internal sensor and logs the temperature from the info-flash calibration. adc_pin reads channel 0 on PA4 and adds the offset measured with the input shorted.

One block clocks every channel from Fsys through a shared divisor and cycle. Each channel keeps its own duty byte and polarity, and the shared remap moves five of the eight pins together. 16-bit cycles and stagger output are not included.

pwm_out drives PA12 at about 400 Hz and steps the duty through 0, 64, 128, 192 and 255, holding each one for a second.

DIV stays 1, and the nearest DL is now rejected when the realised rate is more than two percent from the request. 115200 at the 5.333 MHz reset clock is about 111.1 kbaud, so uart_loopback moves to 9600, which divides exactly.

I2C0 has no DMA registers, so the async path moves each byte from the I2C0 interrupt with the STM32F1-style event sequence: SB, ADDR, TxE, RxNE and BTF. The receive tail masks the level-triggered buffer source, a dropped future aborts with a STOP, and the driver implements embedded-hal-async I2c next to the blocking master. The CH585 controller latches STAR2.BUSY after about 100 ms without traffic even though both lines are idle, and it then ignores START. A fresh frame resets and reprograms the block and sends one address-only start/stop pair to resynchronise the slave before the real transfer. The blocking path uses the same recovery.

SPI0/SPI1 gain an async master whose handler moves bytes on the FIFO half-full, byte-end and count-end events. SPI0 also exposes its peripheral-local half-duplex DMA engine through write_dma/read_dma: checked static byte buffers, chunk re-arming past the 12-bit count, CNT_END completion with DMA_END tracking, and cancellation that quiesces the engine. Full-duplex transfers stay on the interrupt path because the engine queues one direction at a time. SPI1 has no DMA block and shares PWMX_SPI1 with PWMx.

i2c_oled_async drives the SSD1306 with the interrupt-driven master and a 1025-byte frame write that starts with the 0x40 data control byte. spi_async_loopback covers full-duplex async loopback plus SPI0 DMA receive and transmit. pwm_out now breathes an external LED on PA12 and documents that the board LEDs have no PWM function.

Add the async OLED and SPI loopback examples to the tables and their wiring steps, note the half-duplex nature of the SPI0 DMA engine and that I2C0 has no DMA block, and point PWM verification at an external LED because the board LEDs are GPIO-only.

StaticSampleBuffer is the exclusive static storage the ADC's local DMA engine writes one sample per conversion into. It reuses the existing claim-once implementation, which already covers the timer's words and SPI's bytes.

adc_scan_dma samples PA4, PA5 and PA6 in that order, ten passes per transfer, and logs one transfer every 500 ms. PA4 and PA5 can be tied to ground and 3.3 V to check the two ends of the range; PA6 floats.

Record the scan driver, its static 16-bit sample buffers, the polled completion and the end-of-conversion interrupt limitation in the top-level and example READMEs.

SCAN_CFG1 and SCAN_CFG2 are modeled as 4-bit entry arrays, so the sequence is programmed with two small loops instead of thirteen individually named fields, and MAX_CHANNELS derives from the entry counts. The value written is unchanged.

The generated PAC now lives in the public ch32-rs/ch5xx-metapac repository, pinned at v0.1.2 (579d934), so the HAL no longer depends on a sibling ch5xx-data build directory. The snapshot includes the USBHS endpoint fixes, the CH585 pin muxing and the ADC scan registers. Regeneration still happens in ch5xx-data.

The v3c core feature, critical-section support and the atomics opt-out are all in the 0.8.4 release, which is the same tree as the local checkout's v0.8.4 tag, so the crates.io patch is no longer needed and the requirement can name the release directly.

The example now arms overflow reset on the first boot and stops feeding, so the next boot observes a watchdog reset cause before disabling reset and checking the feed path. A board run confirmed both: the chip rebooted after about 6.3 s with `reset cause watchdog`, and a feed cleared the overflow flag, which set again after four seconds. The module documentation's maximum interval was ten times too short; a reload of zero wraps in about 6.3 s at the 5.333 MHz reset clock, not 0.63 s.

Pin ch5xx-metapac to b4e0777, generated after the register access audit in ch5xx-data#8.

IF_CNT_END reads as set for as long as TOTAL_CNT is zero, so enabling IE_CNT_END at construction stormed the interrupt line at priority 0 and starved the caller of Spi::new_async before its first await. A board run with the source armed at construction hung; disabling it made the constructor and both full-duplex transfers complete. Enable only IE_FIFO_OV at construction. The async waits and the DMA arm path now enable IE_CNT_END and IE_DMA_END after a non-zero TOTAL_CNT is programmed, re-check the raw flag to close the arming race, and the handler disables each source after it fires so a completed chunk cannot keep re-asserting. The DMA arm path also programs TOTAL_CNT before the sources are enabled, which is the vendor order.

With PA14 looped to PA15 at 1 MHz, async mode 0 matched 10 bytes and mode 3 matched 40. The DMA receive filled 5000 bytes over two chunks and the DMA transmit completed 5000 bytes, so the chunked re-arm past the 12-bit TOTAL_CNT limit runs in both directions. Master receive mode does not clock 0xFF on MOSI, so the receive check is now that the engine overwrote the whole buffer with one repeated value: the loopback returned 0xE3-0xE4 at every mode and rate. The receive path itself was verified on an unwired remapped MISO pad, whose pull-up reads 0xFF. The README no longer claims 0xFF. Keep the constructor error log and drop the diagnostic progress lines.